1. Field of the Invention
The invention relates to an improved, digital clock delay circuit especially adapted for implementation as a component of an integrated circuit, and more particularly to a compact delay circuit that provides a precisely controlled, delayed version of an input clock signal over a wide range of selectable delays.
Proper operation of certain high-speed, digital integrated circuits, such as, for example, programmable logic arrays, require high frequency clock signals that are slightly delayed with respect to an external clock signal. These delayed clock signals can be used to time various circuit operations and to compensate for the differences in the time required for signal propagation to different parts of the integrated circuit.
2. Description of the Prior Art
There have been a number of proposals in the prior art relating to digital clock delay circuits, also referred to in the art as clock choppers. These proposals include circuits in which a circuit produces a delayed version of a differential input clock with the delay caused by the time it takes to charge and discharge internal circuit capacitances using the internal circuit current. Changing the internal circuit current changes the delay. The following U.S. patents are examples of this type of digital clock delay circuit.
U.S. Pat. No. 4,874,966 to Gehrt et al., "Multivibrator Circuit Having Compensated Delay Time".
U.S. Pat. No. 4,866,314 to Traa, "Programmable High-Speed Digital Delay Circuit".
U.S. Pat. No. 4,862,020 to Cowan et al., "Electronic Delay Control Circuit Having Pulse Width Maintenance".
U S. Pat. No. 4,797,586 to Trass, "Controllable Delay Circuit".
U.S. Pat. No. 4,795,923 to Dobos, "Adjustable Delay Circuit".
U.S. Pat. No. 4,801,827 to Metz, "Adjustable Delay Element For Digital Systems".
U.S. Pat. No. 4,893,036 to Hester et al., "Differential Signal Delay Circuit".
In certain of these prior art circuits, the capacitance of the differential switching transistors is charged and discharged by a controllable current in order to generate a delay. However, the range of selectable delays produced by the charging and discharging of these capacitances is limited unless the circuit capacitance is large, since the acceptable range of current change is limited to a small range around the circuit operating point. It will be appreciated that high speed applications use circuit technology (i.e., bi-polar integrated circuits) that have transistors with small internal capacitances. Thus, in order to obtain sufficient internal capacitance for a large delay range in one circuit, large transistors would be required. But such an approach, like using two stages of delay, requires space on the integrated circuit and is therefore a disadvantageous approach.